The present invention relates generally to overlay measurement techniques, which are used in semiconductor manufacturing processes. More specifically, the present invention relates to techniques for measuring alignment error between different layers or different patterns on the same layer of a semiconductor wafer stack.
The measurement of overlay error between successive patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. Presently, overlay measurements are performed via test patterns that are printed together with layers of the wafer. The images of these test patterns are captured via an imaging tool and an analysis algorithm is used to calculate the relative displacement of the patterns from the captured images.
The most commonly used overlay target pattern is the “Box-in-Box” target, which includes a pair of concentric squares (or boxes) that are formed on successive layers of the wafer. The overlay error is generally determined by comparing the position of one square relative to another square.
To facilitate discussion, FIG. 1 is a top view of a typical “Box-in-Box” target 10. As shown, the target 10 includes an inner box 12 disposed within an open-centered outer box 14. The inner box 12 is printed on the top layer of the wafer while the outer box 14 is printed on the layer directly below the top layer of the wafer. As is generally well known, the overlay error between the two boxes, along the x-axis for example, is determined by calculating the locations of the edges of lines c1 and c2 of the outer box 14, and the edge locations of the lines c3 and c4 of the inner box 12, and then comparing the average separation between lines c1 and c3 with the average separation between lines c2 and c4. Half of the difference between the average separations c1&c3 and c2&c4 is the overlay error (along the x-axis). Thus, if the average spacing between lines c1 and c3 is the same as the average spacing between lines c2 and c4, the corresponding overlay error tends to be zero. Although not described, the overlay error between the two boxes along the y-axis may also be determined using the above technique.
This type of target has a same center of symmetry (COS) for both the x and y structures, as well as for the first and second layer structures. When the target structures are rotated 180° about their COS, they maintain a same appearance. Conventionally, it has been a requirement that both the x and y structures and both the first and second layer structures have a same COS. However, these requirements may be too restrictive under certain conditions. For example, space may be limited on the wafer and a target having x and y structures (or first and second layer structures) with the same COS may not fit into the available space. Additionally, it may be desirable to use device structures for determining overlay, and device structures are not likely to meet this strict requirement.
Although this conventional overlay design has worked well, there are continuing efforts to provide improved techniques for determining or predicting overlay in device structures. For example, targets or device structures that have more flexible symmetry characteristics, as well as techniques for determining overlay with such structures, are needed.